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single port vdsl2 line driver with shutdown ad8398a rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2010 analog devices, inc. all rights reserved. features voltage feedback wide output swing 18.4 v p-p differential, r load, diff = 20 from 12 v supply high output current linear output current of 450 ma peak low distortion ?65 dbc for profile 8b @ 20.4 dbm ?55 dbc for profile 17a @ 14.5 dbm high speed 85 mhz bandwidth (a v diff = 5) applications adsl2+/vdsl2 co/cpe line drivers plc line drivers consumer xdsl modems twisted pair line drivers functional block diagram nc = no connect 1 nc 2 ? in a 3 +in a 4 gnd 11 ? in b 12 nc 10 +in b 9pd1 5 nc 6 nc 7 v ee 8 pd0 15 nc 16 out a 14 v cc 13 out b 07760-001 ? + ? + figure 1. thermally enhanced, 4 mm 4 mm, 16-lead lfcsp_wq typical application diagram v mid * tip ring ad8398a ad8398a 1/2 1/2 *v mid = v cc + v ee 2 07760-002 figure 2. typical vdsl2 application general description the ad8398a comprises two high speed, voltage feedback operational amplifiers. when configured as a differential line driver, the ad8398a is an ideal choice for adsl2+, vdsl2, and power line communications (plc) applications. it has high output current, high bandwidth, and fast slew rate, combined with exceptional multitone power ratio (mtpr) and common- mode stability. the ad8398a is available in a thermally enhanced 4 mm 4 mm, 16-lead lfcsp. the ad8398a incorporates power management functionality via two cmos-compatible control pins, pd0 and pd1. these pins select one of four operating modes: full power, medium power, low power, or complete power-down. in the power-down mode, the quiescent current drops to 0.7 ma. the ad8398a operates in the industrial temperature range of ?40c to +85c.
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ad8398a rev. d | page 2 of 12 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? functional block diagram .............................................................. 1 ? typical application diagram .......................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? absolute maximum ratings............................................................ 4 ? thermal resistance ...................................................................... 4 ? maximum power dissipation ..................................................... 4 ? esd caution.................................................................................. 4 ? pin configuration and function descriptions............................. 5 ? typical performance characteristics ..............................................6 ? applications information .................................................................8 ? power control modes of operation ...........................................8 ? exposed thermal pad connections ...........................................8 ? power supply bypassing ...............................................................8 ? board layout..................................................................................8 ? multitone power ratio..................................................................9 ? lightning and ac power fault ....................................................9 ? outline dimensions ....................................................................... 10 ? ordering guide .......................................................................... 10 ? revision history 9 /10rev. c to rev. d change to general description section ........................................ 1 3/10rev. b to rev. c changes to figure 14........................................................................ 9 12/09rev. a to rev. b changes to figure 13, figure 14, and figure 15 ........................... 9 10/09rev. sp0 to rev. a changed r load to r load, diff throughout ........................................ 1 changes to dc performance, differential input offset voltage parameter, table 1 .............................................................. 3 changes to figure 4.......................................................................... 5 changes to figure 8 and figure 9................................................... 6 changes to exposed thermal pad connections section............ 8 11/08revision sp0: initial version
ad8398a rev. d | page 3 of 12 specifications v s = 12 v, 6 v at t a = 25c, a v diff = 5, r load, diff = 20 , pd1 = 0, pd0 = 0, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit dynamic performance ?3 db bandwidth a v diff = 5, v out = 2 v peak, measured differentially pd1 = 0, pd0 = 0 85 mhz pd1 = 0, pd0 = 1 85 mhz pd1 = 1, pd0 = 0 75 mhz slew rate v out = 4 v peak, measured differentially 600 v/s noise/distortion performance mtpr profile 8b at 20.4 dbm in vdsl2 application ?65 dbc profile 17a at 14.5 dbm in vdsl2 application ?55 dbc off isolation pd1 = 1, pd0 = 1 ?80 dbc input voltage noise f = 100 khz 4.8 nv/hz input current noise f = 100 khz 0.9 pa/hz differential output voltage noise f = 100 khz in vdsl2 applic ation 120 nv/hz dc performance differential input offset voltage ?2 0.1 +2 mv input offset voltage 16 55 mv input bias current 0.5 1 a open-loop gain 63 db common-mode rejection measured differentially ?100 ?74 db input characteristics input resistance f < 100 khz 1.9 m output characteristics differential swing 17.6 18.4 v p-p linear peak output current vdsl2 at 20.4 dbm, mtpr = ?65 dbc 450 ma peak power supply operating range dual supply 6 v single supply 12 v supply current pd1 = 0, pd0 = 0 29 33.2 37 ma pd1 = 0, pd0 = 1 20 22.9 25.5 ma pd1 = 1, pd0 = 0 12 13.3 14.5 ma pd1 = 1, pd0 = 1 0.7 1.1 ma power supply rejection measured differentially ?94 ?74 db power-down pins pd1, pd0 v il referenced to gnd 0.8 v pd1, pd0 v ih referenced to gnd 2 v pd1, pd0 bias current pd1, pd0 = 0 v 15 30 a pd1, pd0 = 3 v 6 17 a enable time pd1, pd0 = (1, 1) ? (0, 0) 60 s disable time pd1, pd0 = (0, 0) ? (1, 1) 600 s
ad8398a rev. d | page 4 of 12 absolute maximum ratings table 2. parameter rating power supplies (v cc ? v ee ) 13.2 v power dissipation (t j max ? t a )/ ja storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c junction temperature 150c maximum power dissipation the maximum safe power dissipation for the ad8398a is limited by its junction temperature (t j ) on the die. the maximum safe t j of plastic encapsulated devices, as determined by the glass transition temperature of the plastic, is 150c. temporarily exceeding this limit may cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package. exceeding this limit for an extended period can result in device failure. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 16-lead lfcsp_wq on a 4-layer board with six vias connecting the exposed pad to the gnd plane layer. ambient temperature (c) maximum power dissipation (w) 0 5 07760-003 4 3 2 1 t j = 150c 6 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 8070 thermal resistance ja is specified with the device soldered on a jedec circuit board and the thermal pad connected to the gnd plane layer using six vias. table 3. thermal resistance package type ja unit 16-lead lfcsp_wq 35.6 c/w figure 3. maximum safe power dissipation vs. ambient temperature, 4-layer jedec board with six thermal vias esd caution
ad8398a rev. d | page 5 of 12 pin configuration and fu nction descriptions nc ? in a +in a gnd nc nc v ee pd0 12 11 10 1 3 4 nc ? in b +in b 9 pd1 2 6 5 7 8 16 out a 15 nc 14 v cc 13 out b top view (not to scale) ad8398a notes 1. nc = no connec t 2. exposed paddle (epad) is floating, not electrically connected internally. 07760-004 figure 4. pin configuration table 4. pin function descriptions pin o. mnemonic description 1, 5, 6, 12, 15 nc no connect. 2 ?in a amplifier a inverting input. 3 +in a amplifier a noninverting input. 4 gnd ground. 7 v ee negative power supply input. 8 pd0 power mode control. 9 pd1 power mode control. 10 +in b amplifier b noninverting input. 11 ?in b amplifier b inverting input. 13 out b amplifier b output. 14 v cc positive power supply input. 16 out a amplifier a output. epad exposed paddle (epad) the exposed paddle is electrically isolated.
ad8398a rev. d | page 6 of 12 typical performance characteristics v cc = 6 v, v ee = ?6 v, unless otherwise stated. 07760-017 closed-loop gain (db) 0.1 1000 100 10 1 frequency (mhz) ?12 ?9 ?6 ?3 0 3 6 9 12 15 18 21 differential common-mode pd1 = 0, pd0 = 0 pd1 = 0, pd0 = 1 pd1 = 1, pd0 = 0 figure 5. small signal differential and common-mode frequency response; a v diff = 5 (see the application circuit in figure 8 ) 07760-018 closed-loop gain (db) 0.1 1000 100 10 1 frequency (mhz) ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 9 12 15 18 differential common-mode pd1 = 0, pd0 = 0 pd1 = 0, pd0 = 1 pd1 = 1, pd0 = 0 figure 6. small signal differential and common-mode frequency response (see the application circuit in figure 9 ) 07760-019 closed-loop gain (db) 0.1 1000 100 10 1 frequency (mhz) ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 differential common-mode pd1 = 0, pd0 = 0 pd1 = 0, pd0 = 1 pd1 = 1, pd0 = 0 figure 7. small signal differential and common-mode frequency response (see the application circuit in figure 10 ) v mid * ad8398a ad8398a 1/2 1/2 *v mid = v cc + v ee 2 07760-014 r load, diff = 20 ? figure 8. typical differential application circuit r load, diff = 20 v mid * ad8398a ad8398a 1/2 1/2 r load, diff = 20 ? *v mid = v cc + v ee 2 07760-015 figure 9. typical differential application circuit with positive feedback r load, diff = 20 v mid * tip ring ad8398a ad8398a 1/2 1/2 *v mid = v cc + v ee 2 07760-016 figure 10. typical vdsl2 application circuit
ad8398a rev. d | page 7 of 12 400 500 600 700 800 900 1000 10 12 14 16 18 20 07760-005 output power (dbm) internal power dissipation (mw) vdsl2 profile 17a pd1 = 0, pd0 = 0 vdsl2 profile 8b pd1 = 0, pd0 = 1 figure 11. internal power dissipation vs. output power 1 10 100 1000 0.01 0.1 1 10 100 07760-007 frequency (mhz) voltage noise (nv/ hz) figure 12. differential output voltage noise vs. frequency in a typical vdsl2 application
ad8398a rev. d | page 8 of 12 applications information power control modes of operation the ad8398a features four power modes: full power, medium power, low power, and complete power-down. two cmos- compatible logic pins (pd0 and pd1) select the power mode. the power modes and associated logic states are listed in table 5 . table 5. power modes pd1 pd0 power mode total supply current (ma) 0 0 full power 33.2 0 1 medium power 22.9 1 0 low power 13.3 1 1 power-down 0.7 exposed thermal pad connections to ensure adequate heat transfer away from the die, connect the exposed thermal pad to a solid plane layer with low thermal resistance. to maximize the operating life of the ad8398a, the thermal design of the system should be kept below the junction temperature of 125c. although it is electrically isolated, the thermal pad typically connects to the ground plane layer. power supply bypassing the ad8398a typically operates on 6 v or +12 v supplies. power the ad8398a circuit with a well-regulated, properly decoupled power supply. to minimize supply voltage ripple and power dissipation, use high quality capacitors with low equivalent series resistance (esr), such as multilayer ceramic capacitors (mlccs). place a decoupling 0.1 f mlcc no more than ? inch away from each of the power supply pins. in addition, a 10 f tantalum capacitor is recommended to provide good decoupling for lower frequency signals and to supply current for fast, large signal changes at the ad8398a outputs. lay out bypass capacitors to keep return currents away from the inputs of the amplifiers. this layout minimizes any voltage drops that can develop due to ground currents flowing through the ground plane. board layout as is the case with all high speed applications, careful attention to printed circuit board (pcb) layout details prevents associated board parasitics from becoming problematic. proper rf design technique is mandatory. the pcb has a ground plane covering all unused portions of the component side of the board to provide a low impedance return path. removing the ground plane on all layers from the area near the input and output pins of the ad8398a reduces stray capacitance. signal lines connecting the feedback and gain resistors should be as short as possible to minimize the inductance and stray capacitance associated with these traces. place termination resistors and loads as close as possible to their respective inputs and outputs. to minimize coupling (crosstalk) through the board, keep input and output traces as far apart as possible. wherever there are complementary signals, provide a symmetrical layout to maximize balanced performance.
ad8398a rev. d | page 9 of 12 multitone power ratio the discrete multitone (dmt) signal used in xdsl systems carries data in discrete tones or bins that appear in the frequency domain in evenly spaced 4.3125 khz intervals. in applications using this type of waveform, multitone power ratio (mtpr) is a commonly used measure of linearity. generally, designers are concerned with two types of mtpr: in band and out of band. in-band mtpr is defined as the measured difference from the peak of one tone that is loaded with data to the peak of an adjacent tone that is intentionally left empty. out-of-band mtpr is defined as the spurious emissions that occur in the receive bands. transmit band power and receive band mtpr are shown in figure 13 , figure 14 , and figure 15 for profile 17a, profile 8b, and adsl2+, respectively. ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 07760-010 frequency (mhz) output power (db) 04 28 61 2 10 1614 2018 figure 13. mtpr of a typical vdsl2 profile 17a dmt test signal, v s = 6 v, output power = 14.5 dbm 07760-020 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 012345678910 output power (dbm/hz) frequency (mhz) figure 14. mtpr of a typical vdsl2 profile 8b dmt test signal, v s = 6 v, output power = 20.4 dbm ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 07760-012 frequency (mhz) output power (db) 0 0.5 1.0 1.5 2.0 2.5 3.0 figure 15. mtpr of a typical adsl2+ dmt test signal, v s = 6 v, output power = 20.4 dbm lightning and ac power fault dsl line drivers are transformer-coupled to the twisted pair telephone line. in this environment, the ad8398a may be subject to large line transients resulting from events such as lightning strikes or downed power lines. additional circuitry is required to protect the ad8398a from possible damage due to these events.
ad8398a rev. d | page 10 of 12 outline dimensions 101408-a 1 0.65 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 2.40 2.35 sq 2.30 4.10 4.00 sq 3.90 0.45 0.40 0.35 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indi c ator 0.35 0.30 0.25 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220-wggd figure 16. 16-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very t hin quad (cp-16-20) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad8398aacpz-r2 ?40c to +85c 16-lead lead frame chip scale package [lfcsp_wq] cp-16-20 AD8398AACPZ-R7 ?40c to +85c 16-lead lead frame chip scale package [lfcsp_wq] cp-16-20 ad8398aacpz-rl ?40c to +85c 16-lead lead frame chip scale package [lfcsp_wq] cp-16-20 1 z = rohs compliant part.
ad8398a rev. d | page 11 of 12 notes
ad8398a rev. d | page 12 of 12 notes ?2008C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07760-0-9 /10(d)

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